Charge-trapping memory devices, which comprise a memory layer sequence of dielectric materials provided for charge-trapping to program the memory cell, especially SONOS (silicon oxide nitride oxide silicon) memory cells comprising oxide-nitride-oxide layer sequences as storage medium, are usually programmed by channel hot electron injection. Charge-trapping memory cells can be structured to enable the storage of two bits of information in each memory cell. U.S. Pat. No. 5,768,192 and U.S. Pat. No. 6,011,725, both of which are incorporated herein by reference, disclose charge-trapping memory cells of a special type of so-called NROM (nitride read only memory) cells, which can be used to store bits of information both at the source and at the drain below the respective gate edges. The programmed cell is read in reverse mode to achieve a sufficient two-bit separation. Erasure is performed by hot hole injection. Further multi-bit charge-trapping memory devices are disclosed in U.S. Patent Application Publication Nos. 2003/0080372 A1 (application Ser. No. 10/283,856), 2003/0148582 A1 (application Ser. No. 10/093,722), and 2003/0161192 A1 (application Ser. No. 09/735,938), and U.S. Pat. No. 6,324,099 B 1, each of which is incorporated herein by reference.
U.S. Patent Application Publication No. 2003/0185055 A1 (application Ser. No. 10/113,356) and a corresponding paper of C. C. Yeh et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory”, 2002 IEEE, both of which are incorporated herein by reference, disclose a non-volatile semiconductor memory cell with electron-trapping erase state, which operates as flash memory and is able to store two bits. The erasure takes place by Fowler-Nordheim tunneling of electrons from either channel or gate electrode into the storage layer of a conventional charge-trapping layer sequence, for example an ONO (oxide nitride oxide) layer sequence. In programming this memory, electric holes are injected into the non-conducting charge-trapping layer. Hot hole injection can be induced at source and drain, which means, at both ends of the channel. This operating method avoids high programming currents.
As the memory layer of charge-trapping memory cells is electrically insulating material, the trapped charge is confined to the sites of the traps, which may be located at either end of the channel. This means that charge-trapping can take place adjacent to either of the source/drain regions of each memory cell. The programming mechanism is improved if the memory layer is additionally confined to limited regions in the vicinity of the two source/drain regions. In this way, a high density of stored information can be obtained.
A high storage density can also be obtained with an array of floating gate memory cells in a NAND architecture. The floating gate is usually formed of an electrically conductive layer between a control gate electrode and the channel region. The charge carriers that are accumulated on the floating gate electrode in the programmed state of the memory cell are not trapped, but are distributed throughout the floating gate so that the electric field vanishes within the electric conductor.
The shrinkability of 2-bit/cell charge-trapping memory devices is essentially limited by two restrictions. A minimal channel length is necessary in order to enable a sufficiently high source/drain voltage; and the arrangement of self-aligned source/drain contacts between the wordlines requires sufficiently thick insulations to guarantee the demanded voltage. An arrangement of charge-trapping memory cells in a NAND array would render an even higher storage density than previous virtual-ground arrays. Therefore, a reduction of the device area would be possible in principle, if the memory cells could be arranged into strings of memory cells. However, this is not actually possible if the usual read/write operation is implemented in the memory device, since the memory cells of a string can only be addressed via further memory cells that are connected in series.